Back-biasing to populate strained layer quantum wells

ABSTRACT

Transistors including a buried channel layer intermediate to a source and a drain and a surface layer intermediate to the buried layer and a gate are operated so as to cause current between the source and the drain to flow predominately through the buried channel layer by applying a back-bias voltage to the transistor. The back-bias voltage modulates a free charge carrier density distribution in the buried layer and in the surface layer.

CROSS-REFERENCE TO RELATED CASES

[0001] This application is a continuation of U.S. patent applicationSer. No. 10/191,006, filed Jul. 8, 2002.

TECHNICAL FIELD

[0002] The invention generally relates to semiconductor devices, and,more particularly, to transistors that include buried channel layers.

BACKGROUND INFORMATION

[0003] Certain microelectronics systems, such as radars, satellites, andcell phones, often require low-power, high-speed and high-densitycircuits having a high signal-to-noise ratio (i.e., low noise). Theserequirements present significant design challenges both at the circuitdesign and at the transistor design level.

[0004] Microelectronic devices that include both analog and digitalcircuits can fulfill all these requirements. Typically, analog circuitsare used to satisfy very high speed and low noise requirements, whiledigital circuits are used to satisfy high density and low powerrequirements.

[0005] Microelectronic devices that include both analog and digitalcircuits on the same silicon substrate typically include surface channelmetal oxide semiconductor field-effect transistors (MOSFET). Surfacechannel analog MOSFETs, however, incur noise problems because noise isinduced at high frequencies due to charge carrier scattering along thesilicon surface channel/gate oxide interface. Thus, for high-speedanalog devices, bipolar transistors are often preferred over surfacechannel field-effect transistors (FETs); bipolar transistor-basedcircuits can exhibit lower noise because conduction does not occur alonga semiconductor-insulator interface. Unfortunately, it is difficult tointegrate both bipolar and surface channel MOSFET devices on a singlesubstrate.

[0006] One way to reduce noise and to integrate digital and analogcircuits is through use of both surface channel and buried channeltransistors. A buried channel FET can have a channel conduction layerthat is buried between doped silicon regions. -A buried channel devicecan exhibit low noise because the conduction occurs in a layer that isspaced. e.g., from a silicon/SiO₂ interface.

[0007] Current flow in a buried channel FET can be controlled bycontrolled doping of a hetero-semiconductor buried layer. The channelmay be formed in a region that includes a narrow bandgap semiconductor.Alternatively, the buried layer can be a quantum well (typically, anultra-thin layer of narrower bandgap semiconductor sandwiched betweentwo layers of larger bandgap semiconductors).

[0008] The conductivity of the buried channel is also controlled by agate bias voltage. In order to operate the transistor, the buried layeroften requires doping control to assist population of the channel withfree charge carriers.

[0009] Some buried channel transistors include a narrow bandgap InGaAsquantum well and an intermediate bandgap AlGaAs layer; the well isdisposed beneath the heterointerface of the InGaAs single quantum wellwith a wide bandgap AlGaAs layer. A thin charge sheet having the sameconductivity type as the wide bandgap layer is formed at theheterointerface. As the magnitude of the gate voltage increases, anenhanced concentration of free charge carriers in the quantum well mayoccur.

[0010] It has been found, however, that driving the gate voltage highenough to accomplish quantum well population typically creates aparallel conduction channel in the surface semiconductor layer, due toformation of an inversion region in the surface layer. The surfaceinversion layer again leads to noise problems since conduction can thenappear at the semiconductor/oxide interface. The surface conduction pathcan also use excess power.

[0011] A further problem arises because buried channel devices oftenutilize advanced doping techniques to ensure that a quantum well ispopulated with charge carriers. To achieve the doping desired in theburied channel layer, the device layers above the buried channel arealso partially doped, thus requiring a complex process of counter-dopingdevice layers.

[0012] Relatively exotic ion implantation processes can be used tocreate effective buried channel devices. For example, a buried channelp-MOSFET device can utilize plasma-doping to fabricate a very shallowp-type channel layer on the top surface of a sub-micrometer buriedchannel p-MOSFET. The buried channel p-MOSFET device formed using thismethod has a higher current drivability and a higher anti-punchthroughresistance.

[0013] Moreover, it is difficult to provide enhanced current drive forboth electrons and holes (i.e., n-type and p-type buried channeldevices) on the same substrate due to added complexity in thesemiconductor fabrication; the required ion implantations andcounter-doping can demand intricate processing steps.

SUMMARY OF THE INVENTION

[0014] The invention involves semiconductor devices that include buriedchannel layers having heterojunction offsets, and involves the use ofback-biasing to control free charge carrier density in a buried channeland a surface layer of the devices. Back-biasing is applied, forexample, via substrate or body-biasing. Features of the inventionprovide, in particular, improved field-effect transistors that include,for example, a strained buried layer of silicon, germanium or SiGe.

[0015] The invention can provide, for example, lower noise, greatercarrier mobility, and both p-channel and n-channel buried layer devicesin a single integrated circuit. For example, a transistor according tothe invention can have improved low-frequency noise (Flicker noise), foruse in oscillator circuits. In particular, the invention can providetransistors well suited to subthreshold and analog operation. Forexample, the invention can provide analog and radio-frequency deviceshaving transistors with increased transconductance, where a buried layerhas carrier mobility superior to carrier mobility in a surface layer.The invention also provides simpler device manufacturing, and caneliminate a need for complex doping steps during fabrication.

[0016] In preferred embodiments, the invention entails devices thatinclude buried strained-layer quantum wells within multi-layerheterostructures, and entails methods of using back-biasing to populatethe buried layers. The back-bias voltage controls preferentialpopulation of charge carriers in the buried layer while leaving asurface layer relatively free of mobile charge carriers.

[0017] Thus, in a first aspect, the invention features a method foroperating one or more transistors. The method includes providing atransistor, which includes a buried channel layer intermediate to asource and a drain and a surface layer intermediate to the buried layerand a gate. The method also includes causing current between the sourceand the drain to flow predominately through the buried channel layer byapplying a back-bias voltage to the transistor. The back-bias voltagemodulates a free charge carrier density distribution in the buried layerand in the surface layer.

[0018] The back-bias voltage can substantially prevent formation of aninversion region in-the surface layer. The back-bias voltage can beselected in cooperation with a gate voltage to cause radio-frequencyoperation of the transistor. A range of gate voltages can be selected tooperate the transistor in a substantially linear drain current versussource voltage condition. The transistor can be operated as an analogdevice, for example, a power device.

[0019] The buried channel layer can include a semiconductor of differentcomposition from neighboring, contiguous layers. The buried layer can bein direct contact with the surface layer, or with additionalintermediate layers. The interface with a neighboring layer can providea heterojunction offset. The offset can assist confinement of freecharge carriers within the buried layer. The buried channel layer canbe, for example, a quantum well.

[0020] The buried channel layer can include a strained semiconductor,and the surface layer can include a semiconductor that is substantiallystrain-free. The buried layer can reside on a relaxed layer, which caninclude silicon and germanium.

[0021] In some embodiments, the strained semiconductor is under tensilestrain, and applying the back-bias voltage causes the buried channellayer to provide an n-type channel. The method can further includeproviding a second transistor associated with the first transistor. Thesecond transistor includes a second buried channel layer, which includesa semiconductor under compressive strain. Applying a second back-biasvoltage to the second transistor causes the second buried channel layerto provide a p-type channel.

[0022] The back-bias voltage in some embodiments is applied to asubstrate, and in other embodiments is applied to an intermediate layeradjacent to the transistor.

[0023] In a second aspect, the invention features a semiconductordevice. The device includes a transistor, which includes a buriedchannel layer and a surface layer. The device also includes a terminalfacilitating application of a voltage to the gate to control a currentbetween the source and the drain. The device includes a charge carriermodulator facilitating application of a back-bias voltage to thetransistor. The back-bias voltage modulates the free charge carrierdensity distribution in the buried layer and in the surface layer. Themodulation of the free charge carrier density distribution causes thecurrent to flow predominately through the buried channel layer.

[0024] The buried channel layer can consist substantially of silicon orgermanium, or can include silicon and germanium. The buried channellayer can include a semiconductor under compressive or tensile strain.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the drawings, like reference characters generally refer to thesame parts throughout the different views. Also, the drawings are notnecessarily to scale, emphasis instead generally being placed uponillustrating the principles of the invention.

[0026]FIG. 1 is a cross-sectional view of a conventional silicon-basedn-channel MOSFET.

[0027] FIGS. 2A-C are energy band diagrams for the conventionaltransistor of FIG. 1 for three different gate voltage settings.

[0028]FIG. 3A is a cross-sectional-view of an embodiment of a transistorconfigured and operated according to the invention.

[0029]FIG. 3B is a cross-sectional view of the transistor of FIG. 3A, aswell as a corresponding energy band diagram for section B-B′ through thetransistor.

[0030]FIG. 3C is a graph of additional drain current versus back-biasvoltage for a fabricated embodiment of a transistor.

[0031]FIG. 4A is a graph of gate capacitance versus gate bias voltagefor the transistor of FIG. 3A.

[0032]FIG. 4B is a graph of gate capacitance versus gate bias voltagefor the n-channel MOSFET of FIG. 1.

[0033]FIG. 5 is a cross-sectional view of an embodiment of a buriedp-channel MOSFET, as well as a corresponding energy band diagram forsection C-C′ through the transistor.

[0034]FIG. 6A is a band diagram for an embodiment of a MOSFET having aburied silicon layer.

[0035]FIG. 6B is a band diagram for an embodiment of a MOSFET having aburied SiGe layer.

DESCRIPTION

[0036] Various features of the invention are well suited to applicationin metal-oxide-semiconductor (MOS) transistors having Si, Si_(1-x)Ge_(x)and/or Ge layers in and/or on a substrate. Preferred embodiments employback-biasing to control the population of free charge carriers in buriedchannel hetero-semiconductor layers relative to the population of freecharge carriers in surface channel layers. The combination ofheterojunction-based buried layers and back-biasing mitigate theproblems of surface channel noise and control of surface channel andburied channel inversion layers, among other advantages.

[0037] The term “MOS” is here used to refer generally to semiconductordevices that include a conductive gate spaced at least by an insultinglayer from a semiconducting channel layer. The terms “SiGe” and“Si_(1-x)Ge_(x)” are here used interchangeably to refer tosilicon-germanium alloys.

[0038] First, to provide a context for description of features of theinvention, the structure and operation of a conventional MOSFET aredescribed, with reference to FIGS. 1-2. FIG. 1 is cross-sectional viewof a conventional (enhancement mode) silicon-based n-channel MOSFET 100.The transistor includes a gate 110, spacers 115, a source 120, a sourcesilicide contact 125, a gate oxide 118, a drain 130, a drain silicidecontact 135 and a silicon substrate 140. During operation, the MOSFET100 can have an electron inversion layer 141 (under appropriate gatebias conditions).

[0039] The gate 110 includes a doped, conductive polycrystalline silicon(“polysilicon”) portion 112 next to the gate oxide 118. The source 120and drain 130 include n-type doped regions formed by diffusion in thep-type substrate. The substrate can include a p-type epitaxial layer, inwhich the MOSFET 100 is fabricated.

[0040] In operation, the gate contact 110 is biased with a gate voltageto control the population of minority carrier electrons in the inversionlayer 141 in the substrate 140 adjacent to the interface with the gateoxide 118. The combination of the gate voltage and a voltage differencebetween the source 125 and drain 135 controls the flow of currentbetween the source 125 and drain 135.

[0041] The MOSFET 100 has a surface channel, which may be defined inphysical or electrical terms. Physically, the surface channel is thep-type semiconductor material that neighbors the gate oxide 118 andwhich joins the source 125 and drain 135. Electrically, the channel isthe inversion layer 141, which provides current flow. Thus, from theelectrical point of view, the presence and condition of the channel arevariable.

[0042] FIGS. 2A-C are energy band diagrams for the conventionaltransistor 100 for three different gate voltage (V_(g)) settings. Thediagrams illustrate the electron energy levels as a function of positionalong section A-A′ through the gate 112, the gate oxide 118 and thechannel. In particular, the semiconductor conduction band edge (E_(c))and valence band edge (E_(v)) in the substrate 140 are shown. Thechannel in the MOSFET 100 is a part of the substrate 140. The Fermilevel (E_(f)) in the conductive gate 110 is displaced relative to theFermi level in the substrate 140 when a voltage is applied to the gate112, due to the voltage drop (equal to V_(g)) that appears across thegate oxide 118.

[0043] The energy band diagrams can illustrate minority carrier behavior(i.e., inversion) and majority carrier behavior (i.e., depletion andaccumulation). The present example illustrates the following gate biasconditions: a gate voltage greater than the MOSFET 100 threshold voltage(V_(t)) (FIG. 2A), a gate voltage equal to the threshold voltage (FIG.2B), and a zero gate bias condition (FIG. 2C).

[0044] The conduction band (E_(c)) edge is pinned at the MOS interface.With zero gate voltage (FIG. 2C), substantially no current flows fromthe source 120 to the drain 130. As the gate bias is increased, theconduction band edge shifts lower in energy relative to the conductionband edge deeper in the substrate 140 until the conduction band crossesthe Fermi level. The gate bias voltage at which an inversion layerbegins to form, and the channel layer begins to conduct, is illustratedin FIG. 2B. This gate voltage is approximately equal to the thresholdvoltage of the MOSFET 100.

[0045] As the gate bias is increased beyond the threshold voltagecondition, the conduction band edge is driven below the Fermi level, asillustrated in FIG. 2A. This causes formation of an inversion layer,i.e., an enhanced density of minority carrier electrons by the interfaceof the gate oxide 118 and silicon substrate 140. For gate voltagesgreater than the threshold voltage of the MOSFET 100, a current flowsbetween the source 120 and the drain 130 when a voltage differenceexists between the source 120 and drain 130. In this manner, themagnitude of the drain current may be controlled by the gate bias in theMOSFET 100.

[0046]FIG. 3A illustrates an embodiment of a transistor 300 configuredand operated according to principles of the invention. FIG. 3A is across-sectional view of a buried channel layer MOSFET 300. The MOSFET300 includes a gate 310, spacers 315, a gate oxide 318, a source 320, asource contact 325, a drain 330, a drain contact 335, a substrate 340, aburied channel layer 350, and a surface layer 360. The gate 310 caninclude, for example, doped polysilicon adjacent to the gate oxide 318and can include other conductive materials, such as a silicide cap.

[0047] The gate oxide 318 can be silicon dioxide, or can include one ormore other dielectric materials. The source 320 and drain 330 can beformed, for example, via dopant implantation, with the spacers 315controlling the extent of dopant diffusion beneath the gate 310.Subsequently, silicide formation can provide the source contact 325 andthe drain contact 335.

[0048] Various voltages can be applied to the MOSFET 300 via variousterminals, including a gate voltage (V_(g)), a source voltage (V_(s)), adrain voltage (V_(d)) and a back-bias voltage (V_(b)). The back-biasvoltage can be applied at the backside of the substrate 340, asdepicted, or at some other location. For example, the MOSFET 300 canreside within a diffused dopant-defined well, with the back-bias voltageapplied to the well. Thus, the back-bias voltage can also be referred toas a body-bias or substrate-bias voltage.

[0049] The buried channel layer 350 is formed from a semiconductorhaving a different composition than the surface layer 360 and thesubstrate 340. Hence, the buried channel layer has hetero-interfaceswith the surface layer 360 and with the substrate 340. Thehetero-interfaces are associated with conduction band and/or valanceband offsets. The offsets can promote the confinement of free chargecarriers within the buried layer 350.

[0050] In some embodiments, the buried channel layer 350 is subject tobiaxial tensile or compressive stress. The induced strain in the buriedchannel layer 350 can be controlled via control of the composition ofthe substrate 340 and/or the buried channel layer 350. Control of thestrain provides additional control over the electrical properties of theburied channel layer, for example, the minority carrier mobility.

[0051] The thickness of the buried layer 350 is chosen to avoid defectformation due to stress while providing sufficient thickness forinversion layer formation. For example, the thickness can be in a rangeof 4 nm to 40 nm. Preferably, the buried layer 350 is undoped or lightlydoped.

[0052] The buried channel layer provides a dominant conduction pathwaybetween the source 320 and the drain 330. For reasons discussed ingreater detail below, application of a back-bias voltage, in cooperationwith a gate voltage, causes an inversion region to form in the buriedlayer 350 while substantially avoiding formation of an inversion regionin the surface layer 360. In preferred MOSFET embodiments, the gatevoltage and the back-bias voltage have the same polarity: typicallypositive for an n-channel device, and negative for a p-channel device.For example, if the source is placed at ground, the back-bias voltageand the gate voltage are positive relative to the source for ann-channel buried layer.

[0053] Use of back-biasing permits control of carrier densitydistribution in the surface and buried layers 360, 350 with little or nodoping of the buried layer 350. As described below with reference toFIG. 3B, the back-bias voltage shifts the energy bands of the surfacelayer 360 and the buried layer 350 to populate the buried layer withminority charge carriers without significantly populating the surfacelayer 360 with minority charge carriers.

[0054] The surface layer 360, the buried layer 350 and the substrate 340can be formed from a variety of materials and materials compositions. Insome embodiments, silicon and germanium are employed. In many of theseembodiments, the substrate includes a SiGe layer or multiple SiGe layersand/or graded composition SiGe layers. The substrate can be formed, forexample, from a silicon wafer, with the SiGe layers grown on the wafer.Other types of wafers can be used as a base for a substrate, e.g.,silicon-on-insulator (SOI) wafers, germanium wafers, glass substratesand laminated substrates.

[0055] For example, the buried layer 350 can be a strained silicon layerepitaxially grown on a relaxed SiGe layer (constituting or at thesurface of layer 340). The relaxed SiGe layer can be formed via methodsknown to those having ordinary skill in the SiGe semiconductor substratearts. Alternatively, the buried layer 350 can be germanium or can beSiGe having a composition that is different from the SiGe of the relaxedlayer.

[0056] For example, the buried channel layer 350 can have a compositionSi_(1-x)Ge_(x) while a relaxed layer portion of the substrate 340 canhave a composition Si_(1-y)Ge_(y). For x>y, the SiGe buried layer 350would be subjected to compressive stress, and would thus exhibit acompressive strain. Moreover, material combinations can be chosen toprovide a p-channel MOSFET, preferably in a compressively strained SiGeburied layer, or a n-channel MOSFET, preferable in a tensilely strainedsilicon layer.

[0057] Moreover, multiple layers can be included to provide bothp-channel and n-channel MOSFETs on a single substrate. One set oftransistors can utilize buried channel layers while the other setutilizes surface channels. Alternatively, both sets of transistors canutilize buried channel layers.

[0058] Referring now to FIG. 3B, an embodiment of operation of theMOSFET 300 of FIG. 3A is described. If the MOSFET 300 is operatedwithout appropriate control of a back-bias voltage, a conductive channelcan form in the surface layer 360, creating an inferior, noisy parallelconduction path. The above described heterostructures, however, exhibitconduction and valence band offsets at the heterostructure interfaces.Energy band offsets, in the conduction band and/or valence band areutilized in conjunction with back-biasing to selectively populate buriedchannel layers with free charge carriers.

[0059]FIG. 3B illustrates a cross-sectional view of the buried n-channelMOSFET 300 and a related energy band diagram 370, which corresponds topositions in the MOSFET 300 along section B-B′. The MOSFET 300 energyband structure exhibits a type II heterojunction offset due to thehetero-buried silicon layer 350. The silicon buried channel layer 350 isalso under tensile biaxial stress due to the lattice mismatch relativeto the relaxed SiGe layer 340. The silicon in the buried channel layer350 is intrinsic, i.e., undoped. In another embodiment, the buriedchannel layer is lightly doped, for example, with a n-type dopant suchas phosphorus or arsenic.

[0060] The energy band diagram 370 illustrates behavior of theconduction band and Fermi level due to inversion layer control, inresponse to two back-bias conditions: zero back-bias condition 380 and apositive back-bias voltage condition 390. With no back-bias voltageapplied (curve 380), the Fermi level lies below the conduction band atall locations along the section through the MOSFET 300. The conductionband edge is pinned in such a manner that the energy levels of theburied channel layer 350 lie above the Fermi level. The surface layer360 and the buried layer 350 have negligible free electron densities.Application of a gate voltage could lead to formation of an inversionlayer in the surface layer, at desired gate voltage operational levels.

[0061] With sufficient positive back-bias voltage (curve 390), a portionof the electron energy states in the quantum well defined by the buriedchannel layer 350 are populated (indicated by shading 395) withoutapplication of a gate voltage. At the same time, the surface layer 360is relatively devoid of free electron charge carriers. Hence, aback-bias voltage can support a gate voltage to obtain source-to-drainconduction predominately via the buried channel layer 350. Further, theback-bias voltage can be selected to provide operation in a desiredrange of gate voltages.

[0062] The conduction band offsets illustrated in FIG. 3B are gradualrather than abrupt, (the latter behavior is illustrated in FIGS. 6A and6B). The gradual variation illustrates the behavior of a typical, realdevice, which has heterojunction interfaces that exhibit a somewhatgradual change in composition, rather than an abrupt composition changeat the heterojunction interface. A compositionally abrupt interface ittypically difficult to achieve. For example, the various elevatedtemperature processing steps typically required for fabrication of adevice can cause some diffusion of atomic species that will blur theinterface.

[0063] A sufficient back-bias voltage can be applied, for example, toplace the buried channel layer 350 near to an inversion condition, andto place the surface layer 360 relatively far from an inversioncondition, when no gate voltage is applied. Application of a small gatevoltage then causes current flow via the buried layer 350 withsubstantially no current flow via the surface layer 360.

[0064] In this manner, back-biasing controls minority carrier density inboth the surface layer 360 and the buried channel layer 350. Thus,proper use of back-biasing can mitigate the limitations of over-drivingthe gate voltage for buried channel devices. Cooperative selection ofback-bias and gate bias voltages can provide gate voltage versussource-to-drain voltage ranges that are compatible with surface channelMOSFET-based devices. These features can ease integration of surfacechannel and buried channel transistors in a single device. Moreover,devices utilizing buried channel layers can utilize the same powersupplies as conventional devices.

[0065] A range of useful back-bias voltage values can be limited byeventual forward biasing of the p-n junctions at the source and drain.This can allow undesirable current flow through the substrate ratherthan through the buried channel. Doping levels in the source, drain andsubstrate can affect the back-bias level that will cause a forward biascondition. With preferred dopant levels, a maximum useful back-biasvoltage in some embodiments is in a range of approximately 0.25 to 0.40volt. A maximum useful back-bias voltage can correspond to a voltage atwhich a source-to-substrate diode begins to contribute significantcurrent to the source-drain characteristics.

[0066] In some embodiments, enhanced population of a buried layerremains possible with forward biasing of the source and/or drain, due toapplication of a back-bias voltage. Increased transconductance, whichcan be of value, for example, for analog and radio frequencyapplications, can be provided even under these conditions.

[0067]FIG. 3C is a graph of additional drain current versus back-biasvoltage, as measured for an embodiment of a n-MOSFET, including a buriedchannel layer,-that was fabricated with a 0.25 μm process (i.e., minimumfeature sizes corresponded to 0.25 μm). The graph shows the additionaldrain current that was associated with application of a correspondingback-bias voltage to the fabricated MOSFET. The back-bias voltage wasapplied between the substrate and ground, and the source of the MOSFETwas tied to ground. The enhanced population of the buried layer causedthe differential gain of the transistor to increase for back-biasvoltages greater than 0 V.

[0068] In an off-state condition, the additional drain current remainedbelow an acceptable 1 nA for back-bias voltages down to −2.5 V.

[0069] For a back-bias voltage of +0.1 V, i.e., at the boundary ofregion “A” and region “B” in the graph, the stand-by off-current of theMOSFET was 1 nA. Thus, a back bias of 0.1 V could be applied withoutsubstantially affecting power consumption of the MOSFET. Also, theFlicker noise could be substantially unaffected at this back-biassetting.

[0070] Back-voltages in a range of +0.1 V to +0.4 V (see region “B”)could be used to provide operation in an “on”, analog mode. Theback-bias can provide, for example, an increase in transconductance andan increase in gain.

[0071] For this embodiment, the back-bias preferably is set closer to+0.1 V (as opposed to +0.4V) for low-frequency oscillator operation ofthe MOSFET; additional current could contribute to Flicker noise.

[0072] If power consumption is of concern, for high-frequency, high-gainoperation of the MOSFET, the back-bias preferably would approach withoutexceeding +0.4 V. If power consumption during on-state operation is notof concern, a back-bias voltage of up to +0.4 and greater could beapplied.

[0073]FIG. 4A is a graph of gate-to-inversion layer capacitance versusgate bias voltage (C-V) for a fabricated MOSFET that corresponded to theburied n-channel layer MOSFET 300 of FIG. 3A. The fabricated MOSFET hadan area of approximately 10×100 μm, and included: a relaxed SiGe bufferlayer of 30% Ge (atomic composition); a strained-Si buried layer ofapproximately 20 nm thickness; a SiGe suface layer of approximately 5 nmthickness (30% Ge); a gate oxide of approximately 4 nm thickness; and apolysilicon gate.

[0074] The curves shown in the graph were obtained via high-frequencyC-V measurements, with three levels of back bias voltage. Themeasurement method was somewhat different from a typical C-V measurementmethod. The source and drain were tied, and the capacitance was measuredbetween the gate and the tied source and drain. The range of lowercapacitance values thus arose from stray capacitances, rather than froma depletion region thickness, as for typical C-V measurements. The rangeof higher capacitance values arose from the presence of an inversionlayer adjacent to the gate oxide interface.

[0075] Three C-V curves corresponding to three fixed back-bias voltagesare shown. A frequency dependence was found to be substantially absent,up to measurement frequencies of at least 1 MHz. For zero back-biasvoltage, the capacitance attains a plateau at a maximum level when agate voltage is attained which causes an inversion layer of electrons toform in the surface layer 360. The buried layer remains relativelyunpopulated at all applied gate bias voltages for the zero back-biascondition. A similar C-V curve is obtained for a negative back-biasvoltage.

[0076] In contrast, for a back-bias substrate voltage of +0.6 V, the C-Vcurve exhibits a large hump (an intermediate level of gate capacitance)intermediate to maximum and minimum capacitance plateaus at higher andlower gate voltages respectively. The hump that appears in the gate biasvoltage range −0.25V to +0.25V corresponds to a range of gate biasvoltages within which an inversion layer forms in the buried layer 350,and within which an inversion layer is substantially absent from thesurface layer 360.

[0077] Thus, a back-bias voltage of +0.6 V, for this embodiment,cooperates with a variable gate voltage to provide a range of gatevoltages within which an inversion layer exists in the buried channellayer 350, but not in the surface layer 360. Proper selection of aback-bias voltage also provides a gate voltage range having asubthreshold gate voltage behavior controlled by weak inversion of theburied layer 350 rather than by weak inversion of the surface layer 360.

[0078] Referring to FIG. 4B, C-V curves for the conventional MOSFET 100are described to contrast the behavior of the conventional MOSFET 100with the behavior of the appropriately back-biased buried channel layerMOSFET 300. FIG. 4B is a graph of three C-V curves of the conventionalMOSFET 100 of FIG. 1. Each curve corresponds to a different, fixedback-bias voltage (the same three back-bias voltages of the graph inFIG. 4A). The C-V curves for the conventional MOSFET 100 exhibit no humpbecause an inversion layer only forms in a surface channel region.

[0079]FIG. 5 is a cross-sectional view of an embodiment of a buriedp-channel MOSFET 500, according to principles of the invention, and acorresponding energy band diagram 570 for a section C-C′ through theMOSFET 500.

[0080] The buried p-channel layer MOSFET 500 includes a buried p-channellayer 550 (formed from germanium), a gate 510, spacers 515, a p-typesource 520, a source silicide contact 525, a p-type drain 530, a drainsilicide contact 535, a relaxed SiGe layer 540 and a relativelystrain-free SiGe surface layer 560. During preferred operation of theMOSFET 500, a negative back-bias voltage is applied for a range ofnegative gate voltages.

[0081] In some embodiments, the substrate is highly doped to minimize avoltage drop between a back-bias contact and a point below the gate.

[0082] The energy band diagram 570 demonstrates carrier behavior under azero back-bias condition 580 and under a negative back-bias voltagecondition 590. Under the zero back-bias condition 580, the conductionband edge is pinned so that the energy levels of the compressivelystrained germanium buried layer 550 lie below the Fermi level. In thiscase, no hole confinement occurs and the compressively strainedgermanium layer 550 remains essentially unpopulated.

[0083] As the back-bias voltage is made negative (curve 590), thevalence band edge bends relative to the Fermi level. A quantity of holeenergy levels become populated within the buried layer 550 (illustratedat 595). Once populated, with application of a source-to-drain voltage,current flows within the germanium buried layer 550 between the source520 and the drain 530. In some embodiments, a back-bias voltage isselected to place the buried layer 550 in a near-populated state whenthe gate voltage is zero.

[0084] Some embodiments apply a back-bias voltage that populates aburied layer, even when no gate voltage is applied. Such embodiments areuseful, for example, in high frequency RF applications. For example,such embodiments can help a gate of an amplifier circuit to respond toan incoming microwave signal.

[0085] As a further example, a device in amplifying mode generally musthave an applied gate bias. Often, the device requires an additional gatebias, which typically must be decoupled from an incoming signal via useof an inductor connected from the gate to the substrate. Connection ofthe inductor to the gate can introduce noise into the incoming signal,and also can cause the loss of some signal to ground. Back biasing thesubstrate can potentially eliminate a need for a bias-strapping inductoron an input line; an inductor can be moved to a less damaging positionon a substrate side of a device.

[0086] Some preferred embodiments of the invention use relaxed SiGelayers grown on silicon substrates. Silicon, germanium and SiGe layerscan be grown via known epitaxial growth techniques. Growth of a buriedlayer of silicon, germanium or SiGe on a SiGe relaxed layer, or SiGe onsilicon, enables production of buried layers of controlled stress anddislocation density. Examples of SiGe substrates, in which the Gecontent can be up to 100%, include:

[0087] A relaxed, uniform composition SiGe layer on a graded compositionSiGe layer atop a Si substrate.

[0088] A relaxed, uniform composition SiGe layer directly atop a Sisubstrate.

[0089] A relaxed, uniform composition SiGe layer on an insulating layerlike SiO₂ atop a Si substrate.

[0090] The hetero-buried channel layers are preferably relatively thin.These channel layers can be single layers of Si, SiGe, or Ge, or amultiple-layer stack consisting of layers of Si, SiGe, or Ge.

[0091] Referring now to FIGS. 6A and 6B, band diagrams for MOSFETshaving buried silicon or buried channel layers are qualitativelyillustrated. FIG. 6A is a band diagram for an embodiment of a MOSFEThaving a buried silicon layer. The buried layer resides on a relaxedSiGe layer and has a SiGe surface layer of similar composition.Preferred embodiments can include a silicon cap to assist formation of ahigh quality gate oxide.

[0092] The silicon buried layer exhibits a type II band gap offset. Withappropriate use of back-biasing, and n-type source and drain doping, anelectron inversion layer is formed in the silicon buried layer toprovide n-type MOSFET operation.

[0093]FIG. 6B is a band diagram for an embodiment of a MOSFET having aburied Si_(1-x)Ge_(x) layer, where x=0.36. The buried layer resides on asilicon substrate and has a silicon cap surface layer. TheSi_(1-x)Ge_(x) buried layer exhibits a type I band gap offset. Withappropriate use of back-biasing, and p-type source and drain doping, ahole inversion layer is formed in the Si_(1-x)Ge_(x) buried layer toprovide p-type MOSFET operation.

[0094] Though MOSFETs for many applications are operated in over-drivemode, i.e., with gate voltage greater than the MOSFET threshold voltage,MOSFETs according to principles of the invention are preferably operatedat lower gate voltages. Preferred embodiments of the invention includetransistors operated in sub-threshold conditions. Many transistorembodiments having improved transconductance are well suited to analogand radio frequency operation. Embodiments intended for low frequencyoperation, for example, as applicable to oscillator circuits, canexhibit reduced Flicker noise.

[0095] Variations, modifications, and other implementations of what isdescribed herein will occur to those of ordinary skill in the artwithout departing from the spirit and the scope of the invention asclaimed. Accordingly, the invention is to be defined not by thepreceding illustrative description but instead by the spirit and scopeof the following claims.

What is claimed is:
 1. A method for operating one or more transistors,comprising: providing a transistor comprising a buried channel layerintermediate to a source and a drain, and a surface layer intermediateto the buried layer and a gate; applying a voltage to the gate tocontrol a current between the source and the drain; and causing thecurrent to flow predominately through the buried channel layer byapplying a back-bias voltage to the transistor to modulate a free chargecarrier density distribution in the buried layer and in the surfacelayer.
 2. The method of claim 1, wherein applying the back-bias voltagecomprises substantially preventing formation of an inversion region inthe surface layer.
 3. The method of claim 1, wherein applying theback-bias voltage comprises selecting the back-bias voltage incooperation with the gate voltage to cause radio frequency operation ofthe transistor.
 4. The method of claim 1, wherein applying the voltageto the gate comprises selecting a range of gate voltages to operate thetransistor in a substantially linear drain current versus source voltagecondition.
 5. The method of claim 1, wherein applying the voltage to thegate comprises operating the transistor as an analog device.
 6. Themethod of claim 5, wherein operating the transistor comprises operatingthe transistor as a power device.
 7. The method of claim 1, wherein theburied channel layer has a heterojunction interface.
 8. The method ofclaim 1, wherein the buried channel layer comprises a strainedsemiconductor.
 9. The method of claim 8, wherein the surface layercomprises a semiconductor that is substantially strain-free.
 10. Themethod of claim 8, wherein the buried layer is intermediate to thesurface layer and a relaxed layer comprising silicon and germanium. 11.The method of claim 8, wherein the strained semiconductor is undertensile strain, and applying the back-bias voltage comprises causing theburied channel layer to provide an n-type channel, and furthercomprising providing a second transistor associated with the firsttransistor and comprising a second buried channel layer comprising asemiconductor under compressive strain, and further comprising applyinga second back-bias voltage to the second transistor to cause the secondburied channel layer to provide a p-type channel.
 12. The method ofclaim 1, wherein the buried channel layer comprises a quantum well. 13.The method of claim 1, wherein applying the back-bias voltage comprisesapplying the back-bias voltage to one of a substrate and an intermediatelayer adjacent to the transistor.
 14. A semiconductor device,comprising: a transistor comprising a buried channel layer intermediateto a source and a drain, and a surface layer intermediate to the buriedlayer and a gate; a terminal facilitating application of a voltage tothe gate to control a current between the source and the drain; and acharge carrier modulator facilitating application of a back-bias voltageto the transistor to modulate a free charge carrier density distributionin the buried layer and in the surface layer to cause the current toflow predominately through the buried channel layer.
 15. The device ofclaim 14, wherein the buried channel layer comprises a semiconductorunder tensile strain.
 16. The device of claim 15, wherein the buriedchannel layer consists substantially of silicon.
 17. The device of claim15, wherein the buried channel layer comprises silicon and germanium.18. The device-of claim 14, wherein the buried channel layer has aheterojunction interface that is associated with a heterojunctionoffset, the offset promoting confinement of free charge carriers in theburied channel layer.
 19. The device of claim 18, wherein theheterojunction offset is one of a type I offset and a type II offset.20. The device of claim 18, wherein the buried channel layer is aquantum well.
 21. The device of claim 14, wherein the device is ananalog device.
 22. The device of claim 14, wherein the buried channellayer comprises a semiconductor under compressive strain.
 23. The deviceof claim 22, wherein the buried channel layer consists substantially ofgermanium.
 24. The device of claim 22, wherein the buried channel layercomprises silicon and germanium.
 25. The device of claim 14, furthercomprising a relaxed layer comprising silicon and germanium, in contactwith the buried layer on a side opposite to the surface layer.
 26. Thedevice of claim 14, wherein the buried channel layer comprises asemiconductor under tensile strain providing an n-type channel, andfurther comprising a second transistor associated with the firsttransistor and comprising a second buried channel layer comprising asecond semiconductor under compressive strain providing a p-typechannel.